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CLLC Resonant Converter Calculator & Walkthrough

Size the resonant tank for a bidirectional, isolated full-bridge CLLC converter (as used in EV onboard chargers and battery energy storage), see the circuit, and work through the parts and signals that make it run.

A CLLC converter is an isolated, bidirectional DC-DC stage built from two mirrored resonant tanks — a Capacitor, an Leakage/resonant inductor, and the transformer's own magnetizing Linductance — one on each side of a high-frequency transformer, each closed out by its own resonant Capacitor. Run it one way and it's a charger; run it the other way and the same hardware discharges back through the same tank. That symmetry is the whole point: unlike a plain LLC converter, whose reverse-direction behavior is at the mercy of uncontrolled transformer parasitics, a CLLC has real resonant elements on both sides, so the switching frequency stays a genuine control handle in either direction. You'll also see it written CLLLC — same circuit, just counting the magnetizing inductance as a third, separate "L" alongside the two leakage inductors.

Both bridges are active full bridges rather than a bridge-plus-diodes: the primary chops the bus into a square wave to excite the tank, and the secondary synchronously rectifies the resulting resonant sine wave — its switches are timed off the tank current's zero crossing rather than a fixed duty cycle. Power transfer is controlled almost entirely by switching frequency, not duty cycle: near the tank's resonant frequency the converter looks resistive and efficient; move the frequency below resonance and it gains (boost); move it above and it bucks.

Full-bridge CLLC power stage

Primary bridge → resonant tank → HF transformer → resonant tank → secondary bridge

S1–S4 chop V_prim into a square wave that excites Crp–Lrp–Lm; the sine-ish tank current is transformed and re-excites the mirrored Crs–Lrs tank on the secondary, where Ss1–Ss4 synchronously rectify it into V_sec. Power flows the other way, unchanged topology, when V_sec > n·V_prim and the roles of the two bridges swap.

Operating point

Output power11.0 kWPrimary (bus) voltage — min700 VPrimary (bus) voltage — max800 VSecondary (battery) voltage — min500 VSecondary (battery) voltage — max700 V

Tank design

Resonant frequency f_r73 kHzInductance ratio k = L_m/L_r4.45Quality factor Q0.40Assumed efficiency η (current estimate)97.0%

Nominal voltage on each side is taken as the midpoint of its min/max range. The secondary tank is mirrored 1:1 through the turns ratio (a = b = 1) — some designs bias it slightly (Infineon's worked example uses a ≈ 0.95, b ≈ 1.05) to fine-tune reverse-mode gain independently.

Turns ratio

1.25

n = V_in,nom / V_out,nom

Voltage gain range (forward)

0.78 – 1.25

M_min = nV_out,min/V_in,max, M_max = nV_out,max/V_in,min

Frequency sweep needed

—

solved from the gain curve below

Equivalent AC load, R_o

41.5 Ω

R_o = (8n²/π²) × V_out,nom²/P

Resonant capacitor, C_rp

132 nF

C_rp = 1 / (2πQf_rR_o)

Resonant inductor, L_rp

36.0 µH

L_rp = 1 / ((2πf_r)²C_rp)

Magnetizing inductance, L_m

160.2 µH

L_m = k × L_rp

Secondary tank, L_rs / C_rs

23.0 µH / 206 nF

L_rs = L_rp/n², C_rs = n²C_rp

Characteristic impedance, Z_r

16.6 Ω

Z_r = √(L_rp/C_rp) = Q × R_o

Primary tank current (at f_r)

25.7 A pk / 18.2 A rms

I_pk ≈ πP / (2ηV_in,nom)

Resonant capacitor voltage stress

426 V pk

V_Crp,pk ≈ I_pk × Z_r

n = Vin_nom / Vout_nom

Ro = (8n²/π²) × Vout_nom² / P

Crp = 1 / (2π Q fr Ro)

Lrp = 1 / ((2π fr)² Crp)

Lm = k × Lrp

Lrs = Lrp / n², Crs = n² × Crp

M(fn) = k·fn² / √{[(1+k)fn² − 1]² + k²Q²fn²(fn²−1)²} , fn = fs/fr

Voltage gain vs. switching frequency

First-harmonic-approximation gain curve for the k and Q chosen above

Gain > 1 (boost) happens below resonance; gain < 1 (buck) happens above it — unity gain at f_r is independent of Q. If the curve folds over instead of falling monotonically as frequency drops, that's the capacitive region: ZVS is lost there, so real designs clamp load/gain to stay out of it (see considerations below).

Parts breakdown

Component roles below follow TI's TIDM-02002 reference design (a 6.6 kW, 500 kHz CLLLC for an EV onboard charger) — real part numbers, not generic placeholders.

Block	Typical components	Role
Primary full bridge	4× SiC/Si MOSFET (e.g. 1200 V CoolSiC)	Chops V_prim into a square wave to excite the tank; ZVS turn-on depends on tank current lagging V_ab.
Primary gate drivers	2× isolated dual-channel driver (UCC21530-Q1)	Level-shifts and drives each leg's high/low FETs with programmable dead time and reinforced isolation.
Primary resonant tank	Film capacitor (C_rp), discrete or leakage inductor (L_rp)	Sets the series resonant frequency together with the secondary tank; stores and releases energy every half-cycle.
Magnetizing inductance	Transformer's own L_m, or an added shunt inductor	Supplies the ZVS commutation energy for the primary FETs during dead time; sized from the k ratio.
HF transformer	Custom ferrite or planar core, turns ratio N	Galvanic isolation, and steps the resonant sine wave between the primary and secondary voltage domains.
Secondary resonant tank	C_rs, L_rs (mirrors the primary tank)	Gives the reverse power-flow path its own controllable resonant frequency, independent of stray transformer parasitics.
Secondary full bridge	4× MOSFET, driven as synchronous rectifiers	Actively rectifies the secondary tank current (or drives it, in reverse mode); timing derives from the tank current's zero crossing.
Secondary gate drivers	2× isolated dual-channel driver (UCC21530-Q1)	Same role as the primary drivers, referenced to the low-voltage/battery ground.
Primary V/I sense	Resistor divider + buffer op-amp (OPA320), comparator (LMV116), shunt	V_prim and I_prim share the MCU's ground, so non-isolated sensing is enough.
Secondary V/I sense	Isolated amplifiers (AMC1311-Q1 for V_sec, AMC1302-Q1 for I_sec)	Cross the isolation boundary to close the CC/CV loop from the battery side.
Tank current sense	Rogowski coil + passive integrator + gain stage (or shunt on the primary)	Wide-bandwidth, isolated sensing of the resonant current, used to time synchronous rectification and for protection.
Controller	Digital controller with high-resolution PWM + hardware comparators (e.g. C2000 TMS320F280049 with CLA)	Runs the CC/CV frequency-control loop and generates the four phase-shifted PWM pairs; on-chip comparators trip PWM directly on overcurrent, no software latency.
DC-link / output caps	Film or electrolytic, one bank per bus	Filters switching-frequency ripple on both the primary bus and the secondary/battery terminals.

Signal inputs vs. outputs

The controller's job reduces to six sensed inputs and eight PWM outputs. Everything else — the CC/CV loop, the frequency command, the synchronous-rectification timing — is built from these.

Direction	Signal	Purpose
Input	V_PRIM	Primary bus voltage — feeds the CV loop reference and protection on the primary side.
Input	V_SEC	Secondary (battery) voltage, sensed through an isolated amplifier — closes the CV loop from the battery side.
Input	I_PRIM	Primary return current — protection and monitoring.
Input	I_{PRIM_TANK}	Primary resonant tank current — protection, and times secondary→primary synchronous rectification during reverse power flow.
Input	I_SEC	Secondary (battery) return current, isolated sense — closes the CC loop.
Input	I_{SEC_TANK}	Secondary resonant tank current — times primary→secondary synchronous rectification during forward power flow.
Output	PRIM_LEG1_H / L	Primary bridge leg 1 gate drive — complementary pair with programmable dead time.
Output	PRIM_LEG2_H / L	Primary bridge leg 2 gate drive — 180° phase-shifted from leg 1; the pair's frequency is the main control variable.
Output	SEC_LEG1_H / L	Secondary bridge leg 1 gate drive — timed off the tank current's zero crossing, advanced to compensate isolator propagation delay.
Output	SEC_LEG2_H / L	Secondary bridge leg 2 gate drive — 180° from leg 1, same synchronous-rectification timing.

Other design considerations

The tank equations above get you a starting point; a handful of second-order effects decide whether the converter actually hits its efficiency target.

Stay out of the capacitive region

Below some frequency, the gain curve stops falling monotonically as you drop below resonance and folds back over — the tank has gone capacitive. Primary ZVS is lost there, switching losses spike, and the slow reverse-recovery of the MOSFET body diodes can push peak currents high enough to damage the switches. Both TI and Infineon respond the same way: clamp the load (or gain target) so the required operating range never dips into that region, rather than chasing gain the tank can't deliver cleanly.

Dead time is an energy budget, not a fixed number. For primary-side ZVS, the energy stored in L_m + L_rp at the moment of turn-off has to exceed the energy needed to charge and discharge the primary switches' output capacitance: ½(Lm+Lrp)·Ipk² > ½(2·Coss)·Vprim². That sets a minimum discharge time tdis > 4·Coss·Vprim / Ipk, and the actual gate dead time is built up from that plus the switches' turn-on/turn-off delays and body-diode conduction time — Infineon's 11 kW SiC design lands on roughly 300 ns.

k and Q trade against each other, not for free. A small k (tight L_m) buys a wide gain range close to resonance, but it also means more magnetizing ripple current and a higher chance of tipping into the capacitive region under a sudden load step. A large k widens the safe operating frequency range but makes for a bulkier transformer and can make hitting peak gain harder. High Q narrows the frequency spread between min and max gain (tighter control range, easier compensator design); low Q gives a flatter, more monotonic gain curve at the cost of needing a wider frequency sweep.

Synchronous rectification is the hard part

The secondary switches must turn on and off in sync with the tank current's zero crossing. Miss it and a circulating current appears on the secondary side, burning efficiency and stressing the FETs with extra drain-to-source current. Two practical approaches show up in the references: a Rogowski coil with a passive RC integrator and comparator to reconstruct current direction digitally, or integrating the voltage across the resonant inductor itself (avoiding a series current transformer entirely). Either way, gate-drive isolators add propagation delay, so the secondary PWM is phase-advanced relative to the primary's falling edge to compensate.

Protect in hardware, not just software. TI's design routes the tank-current comparators (CMPSS, with on-chip DACs for the trip thresholds) straight to the PWM's trip input through the crossbar — an overcurrent event chops the PWM in hardware, with no software loop latency in the path.

Bus ripple sizes your frequency range. A wider PFC bus ripple means the resonant tank has to cover a wider gain window just to ride out that ripple, which directly widens the switching-frequency sweep the controller has to sustain. TI's example: 10% bus ripple needs roughly a 330–670 kHz sweep at a given load; tightening the PFC regulation to 5% ripple narrows that to about 410–570 kHz.

It pays off. Infineon's 11 kW SiC design measured 98.7% efficiency at nominal voltage with synchronous rectification enabled — primary-side conduction losses around 60 W total, secondary around 101 W, switching losses negligible at resonance. Efficiency without SR was measurably lower, especially at light load, where diode conduction drop dominates.

CLLC Resonant Converter Calculator & Walkthrough

Full-bridge CLLC power stage

Turns ratio

Voltage gain range (forward)

Frequency sweep needed

Equivalent AC load, Ro

Resonant capacitor, Crp

Resonant inductor, Lrp

Magnetizing inductance, Lm

Secondary tank, Lrs / Crs

Characteristic impedance, Zr

Primary tank current (at fr)